“Any CMOS imaging system contains an active pixel area and photodetectors that capture photons and convert them into very small photocurrents or electrons. Different parts read the data, including ADC, analog signal processing, user interface digital logic, timing, etc. A small amount of photodiode current in the Femto amp range is integrated into a small charge during the exposure time (opening the shutter), which is converted to a readable voltage by the ADC.
“
By: Majid Dadafshar, Chief Field Application Engineer, ON semiconductor
Summary
Understanding the key challenges of designing power solutions for today’s high resolution, high frame rate CMOS image sensors is a key element in designing an optimized power system solution with LDO (DC-DC, PMIC) that meets every design engineer’s requirements. Power system designers need to know how the power scheme differs in different applications, say, an 8-megapixel (MP) camera versus a 50-megapixel camera, or the difference in frame rates (30 fps) , 60 fps, 120 fps) how to change their power supply design, what frequency requires a high power supply rejection ratio (PSRR), etc. This article is intended to highlight basic considerations before deciding on a powering scheme for any image sensor today.
foreword
Any CMOS imaging system contains an active pixel area and photodetectors that capture photons and convert them into very small photocurrents or electrons. Different parts read the data, including ADC, analog signal processing, user interface digital logic, timing, etc. A small amount of photodiode current in the Femto amp range is integrated into a small charge during the exposure time (opening the shutter), which is converted to a readable voltage by the ADC.
Figure 1. Typical CMOS Imager Architecture
Pixel, Resolution and Transistor Design
Each pixel also has a fill factor, which depends on the percentage of the total pixel area used, and has two parts, a photosensitive and a non-photosensitive part. The photosensitive area captures light, while the non-photosensitive area is used for ADCs, digital blocks, interfaces, and other functions.
The remaining areas are used for horizontal or vertical readout, where a typical READ or WRITE sequence is initiated by the master, generating a START condition on the bus.
The resolution of a CMOS image sensor is the total number of pixel arrays, which consist of many columns and rows. For example, a typical 2-megapixel camera pixel array might be 1600 x 1200.
Figure 2. List of common camera pixels
Some pixels on columns and rows, called dark pixels, are optically black and are used internally for black level correction or row noise correction, which will result in a reduction of the actual active pixel array or actual effective pixels in the array.
There are many different pixel transistor designs (3T, 4T, 5T), such as the four transistor (4T) pixel design shown below. Photodiodes convert the received photons into a small amount of electrical charge, and there are switches to select different columns and rows. In order not to interfere with the reading of the photodiode, a high impedance amplifier on the photodiode junction is used as a source follower amplifier (TIA/SIA). In order not to interfere with the photodiode readings, high impedance amplifiers at the photodiode junctions are used as source follower amplifiers (TIA/SF Amp) to drive each column bus.
Figure 3. Example of a Four-Transistor Design
Each pixel voltage is read one row at a time and put into column capacitors (Cs), which are then read using column decoders and multiplexers.
Figure 4. Example of selected rows and columns
Frame and line conversion
Frame rate measures the speed at which a complete image is captured and the array is read out for processing, with a typical frequency range of 30-120 hertz (Hz). The image sensor can be a high frame rate device (>60 fps) for slow motion playback, or a low frame rate device for motion blur effects (
Rate can also be limited or affected by shutter speed, which controls how long the image sensor collects light, or a possible “dark period” that occurs after the last line is used for horizontal blanking, sync timing, or other purposes. Program the time interval.
We can calculate the frequency of the highest PSRR required for a given frame rate (15, 30 or 60). – For example, a 4-megapixel camera – and design an LDO with the required PSRR for calculating the frequency.
Figure 5. Effects of different frame rates and horizontal frequencies
The frame rate is about 75% of the readout rate, and the other 25% is used as idle time for other processing, such as changing aperture, exposure time calculation, lens autofocus (AF), image processing, memory write speed, etc. For still images and video, the frame readout is performed in a line-sequential fashion, and finally, the entire frame is collected in a buffer and the complete image is rendered.
Image Sensor Power Rails
CMOS image sensors typically require three different power rails to power the analog rail (AVDD), the interface (DOVDD), and the digital rail (DVDD). The standard voltage for the analog power rail is 2.8 V, the interface power rail is 2.8 V or 1.8 V, and the digital power rail is 1.8 V or 1.2 V.
To improve the noise performance of the CMOS image sensor, we can place a large bypass capacitor before the power supply pin.
Reducing the fluctuation of each power rail also improves the noise performance of CMOS image sensors.In general, analog power rails
is the most noise sensitive track, followed by the digital track, which is also sensitive to noise.
Power Supply Rejection Ratio (PSRR)
PSRR provides a measure of how well an LDO can reject ripple, or how well it blocks noise generated by the power rails only at the input of the LDO. The higher the PSRR, the more power supply noise or ripple can be blocked. These ripples may come from the input power supply with 50/60 Hz ripple, the switching frequency of DC-DC, or the ripple due to different circuits sharing the input power supply.
Figure 6. Example of noise from input to output of an LDO
The feedback loop of the LDO typically controls the PSRR of the system at frequencies below 100 kHz. So make sure to choose an appropriate LDO. For frequencies above 100 kHz, appropriate selection of passive components and PCB layout/location controls PSRR.
Figure 7. PSRR Behavior vs. Frequency of a Typical LDO
When designing the PCB, care should be taken to keep the current loop tight to reduce parasitic inductance and ripple between the power rail and the camera rail. Using a clean bias or higher margin between Vin and Vo can also increase the PSRR performance capability.
Low PSRR performance or any noise on the analog rails can cause noise on the power rails to enter the output signal path through the high gain source follower amplifier circuit, causing unwanted horizontal ripples in the captured image.
Figure 8. Example of Noise on an Analog Rail
Normal LDOs have low PSRR at high frequencies, which should be sufficient for normal cameras, but for high resolution and high frame rate image sensors in the 50-200 MP range, a specific series of LDOs are definitely needed, at lower The PSRR is greater than 90 dB in the frequency range (up to 10 kHz) and 45 dB in the 1-3 MHz frequency range to reduce ripple during frame and line rate transitions.
Sensor Frame and Line Rate vs. Power Load
It’s worth noting that both frame rate (30-120 fps) and line rate (22-44 kHz) place a dynamic load on the image sensor, creating undershoot and overshoot on the 2.8 V analog rail.
During each new frame or new row transition, current is drawn like a step load. For example, during a frame or row read, or between each frame or row read, the power scheme (LDO) needs to handle load changes of several hundred mA during each frame and row transition, but There are no large fluctuations on its output voltage rail.
For camera decoupling, body capacitors are required to have the lowest impedance around the line and frame frequencies for best system performance.
LDO output noise (μVRMS)
Depending on the design of the image sensor, each pixel has a charge saturation or full well capacity – the amount of charge (in electrons) a pixel can hold before it saturates. For any image sensor, dynamic range (dB) is defined as the brightest and darkest parts of an image that can be captured simultaneously.
Figure 9. Example of pixel capacity and noise floor
At the output of any LDO, the lower the spectral noise density between 10 Hz and 1 MHz, the more important it is, the less noise is transferred into the CMOS image sensor, resulting in a higher dynamic range for a given pixel .
Figure 10. Typical LDO Output Noise Density
It is critical to find the signal-to-noise ratio (SNR) information of a CMOS image sensor and design the system so that the overall ripple and noise are at least 40 dB below the noise threshold of the sensor.
Summarize
When designing LDO power supply solutions for image sensors of different specifications, there are different problems to be solved, such as 4 million pixels is different from 40 million pixels, 30 frames is different from 120 frames, or high dynamic range is different from low dynamic range, and many more. We achieve the maximum allowable frame rate for high resolution cameras through the maximum data rate capability provided by the Internet Service Provider (ISP) and the number of C/D-PHY MIPI lanes used. Taking into account the calculated maximum PSRR required for the highest frame rate frequency, and the required RMS noise density for a given image sensor with known SNR, can help us design an optimized power system to meet today’s high resolution and high frame rate CMOS image sensor requirements.
Using an LDO scheme with high PSRR, low RMS noise at higher frequencies, and suitable passives with specific impedances at given vertical and horizontal frequencies can help improve the overall noise performance of CMOS image sensors and reduce power moiré, resulting in a captured image with less unwanted horizontal moiré.
“Any CMOS imaging system contains an active pixel area and photodetectors that capture photons and convert them into very small photocurrents or electrons. Different parts read the data, including ADC, analog signal processing, user interface digital logic, timing, etc. A small amount of photodiode current in the Femto amp range is integrated into a small charge during the exposure time (opening the shutter), which is converted to a readable voltage by the ADC.
“
By: Majid Dadafshar, Chief Field Application Engineer, ON semiconductor
Summary
Understanding the key challenges of designing power solutions for today’s high resolution, high frame rate CMOS image sensors is a key element in designing an optimized power system solution with LDO (DC-DC, PMIC) that meets every design engineer’s requirements. Power system designers need to know how the power scheme differs in different applications, say, an 8-megapixel (MP) camera versus a 50-megapixel camera, or the difference in frame rates (30 fps) , 60 fps, 120 fps) how to change their power supply design, what frequency requires a high power supply rejection ratio (PSRR), etc. This article is intended to highlight basic considerations before deciding on a powering scheme for any image sensor today.
foreword
Any CMOS imaging system contains an active pixel area and photodetectors that capture photons and convert them into very small photocurrents or electrons. Different parts read the data, including ADC, analog signal processing, user interface digital logic, timing, etc. A small amount of photodiode current in the Femto amp range is integrated into a small charge during the exposure time (opening the shutter), which is converted to a readable voltage by the ADC.
Figure 1. Typical CMOS Imager Architecture
Pixel, Resolution and Transistor Design
Each pixel also has a fill factor, which depends on the percentage of the total pixel area used, and has two parts, a photosensitive and a non-photosensitive part. The photosensitive area captures light, while the non-photosensitive area is used for ADCs, digital blocks, interfaces, and other functions.
The remaining areas are used for horizontal or vertical readout, where a typical READ or WRITE sequence is initiated by the master, generating a START condition on the bus.
The resolution of a CMOS image sensor is the total number of pixel arrays, which consist of many columns and rows. For example, a typical 2-megapixel camera pixel array might be 1600 x 1200.
Figure 2. List of common camera pixels
Some pixels on columns and rows, called dark pixels, are optically black and are used internally for black level correction or row noise correction, which will result in a reduction of the actual active pixel array or actual effective pixels in the array.
There are many different pixel transistor designs (3T, 4T, 5T), such as the four transistor (4T) pixel design shown below. Photodiodes convert the received photons into a small amount of electrical charge, and there are switches to select different columns and rows. In order not to interfere with the reading of the photodiode, a high impedance amplifier on the photodiode junction is used as a source follower amplifier (TIA/SIA). In order not to interfere with the photodiode readings, high impedance amplifiers at the photodiode junctions are used as source follower amplifiers (TIA/SF Amp) to drive each column bus.
Figure 3. Example of a Four-Transistor Design
Each pixel voltage is read one row at a time and put into column capacitors (Cs), which are then read using column decoders and multiplexers.
Figure 4. Example of selected rows and columns
Frame and line conversion
Frame rate measures the speed at which a complete image is captured and the array is read out for processing, with a typical frequency range of 30-120 hertz (Hz). The image sensor can be a high frame rate device (>60 fps) for slow motion playback, or a low frame rate device for motion blur effects (
Rate can also be limited or affected by shutter speed, which controls how long the image sensor collects light, or a possible “dark period” that occurs after the last line is used for horizontal blanking, sync timing, or other purposes. Program the time interval.
We can calculate the frequency of the highest PSRR required for a given frame rate (15, 30 or 60). – For example, a 4-megapixel camera – and design an LDO with the required PSRR for calculating the frequency.
Figure 5. Effects of different frame rates and horizontal frequencies
The frame rate is about 75% of the readout rate, and the other 25% is used as idle time for other processing, such as changing aperture, exposure time calculation, lens autofocus (AF), image processing, memory write speed, etc. For still images and video, the frame readout is performed in a line-sequential fashion, and finally, the entire frame is collected in a buffer and the complete image is rendered.
Image Sensor Power Rails
CMOS image sensors typically require three different power rails to power the analog rail (AVDD), the interface (DOVDD), and the digital rail (DVDD). The standard voltage for the analog power rail is 2.8 V, the interface power rail is 2.8 V or 1.8 V, and the digital power rail is 1.8 V or 1.2 V.
To improve the noise performance of the CMOS image sensor, we can place a large bypass capacitor before the power supply pin.
Reducing the fluctuation of each power rail also improves the noise performance of CMOS image sensors.In general, analog power rails
is the most noise sensitive track, followed by the digital track, which is also sensitive to noise.
Power Supply Rejection Ratio (PSRR)
PSRR provides a measure of how well an LDO can reject ripple, or how well it blocks noise generated by the power rails only at the input of the LDO. The higher the PSRR, the more power supply noise or ripple can be blocked. These ripples may come from the input power supply with 50/60 Hz ripple, the switching frequency of DC-DC, or the ripple due to different circuits sharing the input power supply.
Figure 6. Example of noise from input to output of an LDO
The feedback loop of the LDO typically controls the PSRR of the system at frequencies below 100 kHz. So make sure to choose an appropriate LDO. For frequencies above 100 kHz, appropriate selection of passive components and PCB layout/location controls PSRR.
Figure 7. PSRR Behavior vs. Frequency of a Typical LDO
When designing the PCB, care should be taken to keep the current loop tight to reduce parasitic inductance and ripple between the power rail and the camera rail. Using a clean bias or higher margin between Vin and Vo can also increase the PSRR performance capability.
Low PSRR performance or any noise on the analog rails can cause noise on the power rails to enter the output signal path through the high gain source follower amplifier circuit, causing unwanted horizontal ripples in the captured image.
Figure 8. Example of Noise on an Analog Rail
Normal LDOs have low PSRR at high frequencies, which should be sufficient for normal cameras, but for high resolution and high frame rate image sensors in the 50-200 MP range, a specific series of LDOs are definitely needed, at lower The PSRR is greater than 90 dB in the frequency range (up to 10 kHz) and 45 dB in the 1-3 MHz frequency range to reduce ripple during frame and line rate transitions.
Sensor Frame and Line Rate vs. Power Load
It’s worth noting that both frame rate (30-120 fps) and line rate (22-44 kHz) place a dynamic load on the image sensor, creating undershoot and overshoot on the 2.8 V analog rail.
During each new frame or new row transition, current is drawn like a step load. For example, during a frame or row read, or between each frame or row read, the power scheme (LDO) needs to handle load changes of several hundred mA during each frame and row transition, but There are no large fluctuations on its output voltage rail.
For camera decoupling, body capacitors are required to have the lowest impedance around the line and frame frequencies for best system performance.
LDO output noise (μVRMS)
Depending on the design of the image sensor, each pixel has a charge saturation or full well capacity – the amount of charge (in electrons) a pixel can hold before it saturates. For any image sensor, dynamic range (dB) is defined as the brightest and darkest parts of an image that can be captured simultaneously.
Figure 9. Example of pixel capacity and noise floor
At the output of any LDO, the lower the spectral noise density between 10 Hz and 1 MHz, the more important it is, the less noise is transferred into the CMOS image sensor, resulting in a higher dynamic range for a given pixel .
Figure 10. Typical LDO Output Noise Density
It is critical to find the signal-to-noise ratio (SNR) information of a CMOS image sensor and design the system so that the overall ripple and noise are at least 40 dB below the noise threshold of the sensor.
Summarize
When designing LDO power supply solutions for image sensors of different specifications, there are different problems to be solved, such as 4 million pixels is different from 40 million pixels, 30 frames is different from 120 frames, or high dynamic range is different from low dynamic range, and many more. We achieve the maximum allowable frame rate for high resolution cameras through the maximum data rate capability provided by the Internet Service Provider (ISP) and the number of C/D-PHY MIPI lanes used. Taking into account the calculated maximum PSRR required for the highest frame rate frequency, and the required RMS noise density for a given image sensor with known SNR, can help us design an optimized power system to meet today’s high resolution and high frame rate CMOS image sensor requirements.
Using an LDO scheme with high PSRR, low RMS noise at higher frequencies, and suitable passives with specific impedances at given vertical and horizontal frequencies can help improve the overall noise performance of CMOS image sensors and reduce power moiré, resulting in a captured image with less unwanted horizontal moiré.
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