RISC-V Challenges and Opportunities: How to Make Money with RISC-V?

Recently, foreign media semiengineering conducted an interview with industry-related companies on many issues of RISC-V. The interviewees included: Ben Levine, senior director of product management of Rambus security department, Jerry Ardizzone, vice president of global sales at Codasip, Megan Wachs, vice president of engineering at SiFive, and Bluespec CTO of Rishiyur Nikhil.

The following is part of the interview:

Q: How to make money through RISC-V?

Nikhil: We develop systems around RISC-V cores to help bring those cores to market. We have a lot of open source cores and these are getting a lot of attention, it’s not making money on the core itself. It’s in the surrounding things.

Ardizzone: We’re a pure processor IP company, and we can’t make money in this business on our own. We need RISC-V to succeed. It needs to be widely adopted, and we need a strong third-party ecosystem. Therefore, in semiconductor IP, the largest segment is processor IP. We’re in this business, our job is to go out and get some market share, and we’re not going to do that unless RISC-V is successful. The market is vast, so we just need to deliver great products that differentiate and provide value to our customers.

Levine: We’re actually participating in the RISC-V ecosystem in a few different ways. One is that we produce secure IP. Our main business is selling security IP, which is the programmable trust foundation for companies that make Chips. Our latest generation uses RISC-V processors developed specifically for security. RISC-V is really a game changer for us as it allows us to control the architecture and the microarchitecture, and to do things that enhance security that we couldn’t do with third-party processor IP. Another way we are involved with RISC-V is that there are some security solutions that are tied to specific processors and we produce security IP that works with any RISC-V cpu.

Q: What is the biggest competition RISC-V faces? Is it ARM or MIPS, or the ecosystem itself?

Wachs: I think the biggest competition is actually that a lot of companies want to design their own RISC-V CPUs. After these companies read the RISC-V specification, they will think: Designing RISC-V is not difficult and fun, and then they are ready to do it themselves. However, when I reached about two-thirds of the way, I began to realize that it was not as simple as I thought.

Ardizzone: From my perspective, the biggest competition for us is obviously Arm. They own about 80% of the market. So if we want to be successful and grow, we need to capture some market share and that’s our mission. But we also have some very strong competitors that will become our main competitors as they grow.

Levine: On the Wachs point, we did develop our own RISC-V CPU, and it wasn’t easy, and we did it only because we had a good reason to do it, because we had the security features that we needed. Added at the microarchitectural level. If not, we would still like to be able to buy off-the-shelf IP directly from other companies that specialize in the technology and have already developed IP.

Nikhil: Probably Arm in the short term. By short-term I mean the next five years or so. In a typical disruptive scenario, what happens now is you need to start at the bottom, and then you go for the embedded, small device controllers, and those are where Arm dominates, and that’s the initial competition. But over time, companies like vector gues emerged – for example, esperanto, which was in the business of high-end processors.

Q: Will the entire ecosystem be fragmented because RISC-V has too many participants?

Nikhil: I’m not too worried about that. At least so far, the ISA has been tightly controlled and governed by the RISC-V Foundation. So while there are a lot of players, the definition of a RISC-V processor comes from the foundation and is about to undergo rigorous tests that must be passed before you can legally call it a RISC-V processor for the foundation Make sure that what you’re building is actually RISC-V. So from that perspective, I’m not too worried about disagreements on this front.

Levine: I’m not too worried about fragmentation, too much self-customization means you give up all the advantages of using RISC-V in the first place. So those who go their own way quickly get stuck and lose ecological support. There really isn’t much incentive to do this.

Nikhil: One of the very unique things about the RISC-V ISA is that it was designed with this in mind. As such, it is extremely modular and designed with reserved opcode space, reserved mechanisms to scale to larger instruction lengths, etc. So people doing extensions don’t add stuff at will. They are operating in a certain structure and fitting in a certain structured way. This limits fragmentation.

Q: At the RISC-VFoundation conference a year ago, one of the concerns from users was the lack of tools, inconsistent compilers, and missing security. Can all of these be solved?

Nikhil: Yes. Fragmentation issues are mostly about whether you do the same thing when you run the same program. There is general consensus on this point. Software will naturally follow. The fact of having a unified hardware base naturally brings together all these software efforts to align with it.

Wachs: Working with industry providers is our number one priority, and I’ve seen a lot of different companies understand and support RISC-V. We work with debug tool companies Segger and Lauterbach, and there are RISC-V Foundation members everywhere. It’s a huge community, and all software tool developers see support for RISC-V in their favor.

Ardizzone: True, if we don’t have great tools, it won’t be successful. So we’ve been thinking about developing tools. Not just hardware or implementation. For example, a lot about the C compiler. We have invested in this. We employ a lot of people who are focused on building what we want to be the world’s best C compiler for RISC-V, but we can’t do it alone. The entire industry needs to provide different options for different customers. Take LLVM as an example. Some people want to use the GNU compiler. So whatever you like, whatever your internal strategy. We need full support. And they have to be first-class tools. There is a lot of momentum right now. We had a high turnout at the RISC-V roadshow in China, and many 3rd party vendors came and supported this. There is a lot of interest and a lot of questions about software performance and tool robustness. We have come a long way as an industry over the past two years.

Levine: We’re seeing a really virtuous cycle in RISC-V. As ISA adoption has grown, so has the interest in the tools, and the tools have gotten better. There is growing interest as tools improve and the ecosystem expands. And the cycle continues. The momentum is great and will continue to grow.

Recently, foreign media semiengineering conducted an interview with industry-related companies on many issues of RISC-V. The interviewees included: Ben Levine, senior director of product management of Rambus security department, Jerry Ardizzone, vice president of global sales at Codasip, Megan Wachs, vice president of engineering at SiFive, and Bluespec CTO of Rishiyur Nikhil.

The following is part of the interview:

Q: How to make money through RISC-V?

Nikhil: We develop systems around RISC-V cores to help bring those cores to market. We have a lot of open source cores and these are getting a lot of attention, it’s not making money on the core itself. It’s in the surrounding things.

Ardizzone: We’re a pure processor IP company, and we can’t make money in this business on our own. We need RISC-V to succeed. It needs to be widely adopted, and we need a strong third-party ecosystem. Therefore, in semiconductor IP, the largest segment is processor IP. We’re in this business, our job is to go out and get some market share, and we’re not going to do that unless RISC-V is successful. The market is vast, so we just need to deliver great products that differentiate and provide value to our customers.

Levine: We’re actually participating in the RISC-V ecosystem in a few different ways. One is that we produce secure IP. Our main business is selling security IP, which is the programmable trust foundation for companies that make chips. Our latest generation uses RISC-V processors developed specifically for security. RISC-V is really a game changer for us as it allows us to control the architecture and the microarchitecture, and to do things that enhance security that we couldn’t do with third-party processor IP. Another way we are involved with RISC-V is that there are some security solutions that are tied to specific processors and we produce security IP that works with any RISC-V cpu.

Q: What is the biggest competition RISC-V faces? Is it ARM or MIPS, or the ecosystem itself?

Wachs: I think the biggest competition is actually that a lot of companies want to design their own RISC-V CPUs. After these companies read the RISC-V specification, they will think: Designing RISC-V is not difficult and fun, and then they are ready to do it themselves. However, when I reached about two-thirds of the way, I began to realize that it was not as simple as I thought.

Ardizzone: From my perspective, the biggest competition for us is obviously Arm. They own about 80% of the market. So if we want to be successful and grow, we need to capture some market share and that’s our mission. But we also have some very strong competitors that will become our main competitors as they grow.

Levine: On the Wachs point, we did develop our own RISC-V CPU, and it wasn’t easy, and we did it only because we had a good reason to do it, because we had the security features that we needed. Added at the microarchitectural level. If not, we would still like to be able to buy off-the-shelf IP directly from other companies that specialize in the technology and have already developed IP.

Nikhil: Probably Arm in the short term. By short-term I mean the next five years or so. In a typical disruptive scenario, what happens now is you need to start at the bottom, and then you go for the embedded, small device controllers, and those are where Arm dominates, and that’s the initial competition. But over time, companies like vector gues emerged – for example, esperanto, which was in the business of high-end processors.

Q: Will the entire ecosystem be fragmented because RISC-V has too many participants?

Nikhil: I’m not too worried about that. At least so far, the ISA has been tightly controlled and governed by the RISC-V Foundation. So while there are a lot of players, the definition of a RISC-V processor comes from the foundation and is about to undergo rigorous tests that must be passed before you can legally call it a RISC-V processor for the foundation Make sure that what you’re building is actually RISC-V. So from that perspective, I’m not too worried about disagreements on this front.

Levine: I’m not too worried about fragmentation, too much self-customization means you give up all the advantages of using RISC-V in the first place. So those who go their own way quickly get stuck and lose ecological support. There really isn’t much incentive to do this.

Nikhil: One of the very unique things about the RISC-V ISA is that it was designed with this in mind. As such, it is extremely modular and designed with reserved opcode space, reserved mechanisms to scale to larger instruction lengths, etc. So people doing extensions don’t add stuff at will. They are operating in a certain structure and fitting in a certain structured way. This limits fragmentation.

Q: At the RISC-VFoundation conference a year ago, one of the concerns from users was the lack of tools, inconsistent compilers, and missing security. Can all of these be solved?

Nikhil: Yes. Fragmentation issues are mostly about whether you do the same thing when you run the same program. There is general consensus on this point. Software will naturally follow. The fact of having a unified hardware base naturally brings together all these software efforts to align with it.

Wachs: Working with industry providers is our number one priority, and I’ve seen a lot of different companies understand and support RISC-V. We work with debug tool companies Segger and Lauterbach, and there are RISC-V Foundation members everywhere. It’s a huge community, and all software tool developers see support for RISC-V in their favor.

Ardizzone: True, if we don’t have great tools, it won’t be successful. So we’ve been thinking about developing tools. Not just hardware or implementation. For example, a lot about the C compiler. We have invested in this. We employ a lot of people who are focused on building what we want to be the world’s best C compiler for RISC-V, but we can’t do it alone. The entire industry needs to provide different options for different customers. Take LLVM as an example. Some people want to use the GNU compiler. So whatever you like, whatever your internal strategy. We need full support. And they have to be first-class tools. There is a lot of momentum right now. We had a high turnout at the RISC-V roadshow in China, and many 3rd party vendors came and supported this. There is a lot of interest and a lot of questions about software performance and tool robustness. We have come a long way as an industry over the past two years.

Levine: We’re seeing a really virtuous cycle in RISC-V. As ISA adoption has grown, so has the interest in the tools, and the tools have gotten better. There is growing interest as tools improve and the ecosystem expands. And the cycle continues. The momentum is great and will continue to grow.

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