“Reliable voltage supervisor ICs have always been an industry requirement because they can improve system reliability and improve system performance during voltage transients and power failures. semiconductor manufacturers are also continuously improving the performance of voltage supervisor ICs.
“
Reliable voltage supervisor ICs have always been an industry requirement because they can improve system reliability and improve system performance during voltage transients and power failures. Semiconductor manufacturers are also continuously improving the performance of voltage supervisor ICs.
The supervisor IC requires a power-on reset (VPOR) to generate an unambiguous or reliable reset signal, and the state of the reset signal is indeterminate until this minimum supply voltage is reached. Generally, we call this a reset glitch. There are mainly two different topologies for the reset pin, open-drain and push-pull (Figure 1), both of which use an NMOS as the pull-down MOSFET.
Figure 1. Open-Drain and Push-Pull Configurations for Reset Topologies
Figure 2. How the reset voltage is related to the pull-up voltage (VPULLUP) proportionally, resulting in what is commonly referred to as a reset glitch
During power-up, if the supply voltage falls below VPOR, there is not enough voltage to drive the internal MOSFET, so the MOSFET turns off. At this point, the supervisor cannot control the reset voltage. The reset voltage will be the same as the pull-up voltage (VPULLUP) increases proportionally. And once the supply voltage is higher than VPORthe internal MOSFET will drive the RESET pin into an active state.
Voltage supervisors can be used to monitor the low power rails of FPGAs, ASICs or DSPs down to 1V. In low supply voltage processors, I/Os are very sensitive to logic levels and their VIHCan be as low as 0.5V, as shown in Figure 3.
Figure 3. Supervisor Interface to Low Supply Voltage ASIC/FPGA/DSP
During power-up, the FPGA, ASIC, or DSP needs to be in the RESET state until all power rails are stable. When VDD is below VPOR, the RESET pin may experience a glitch that may trigger an unknown state of the FPGA. Once VDD is higher than VPORthe internal MOSFET turns on and connects RESET to GND and causes the RESET pin to output the correct logic low level.
Figure 4. Power-Up Sequence with Glitch Reset Signal
As the electronics industry moves toward low-voltage semiconductors, analog chip makers are also striving to achieve glitch-free monitors based on traditional monitors. Manufacturers can reduce V by improving the processPORbut implementing a truly glitch-free monitor requires an entirely new architecture.
Currently, system engineers use external circuits with traditional supervisors to emulate the glitch-free supervisory function shown in Figure 5. Adding a standard JFET configured as a source follower accomplishes this, and the voltage at the source will depend on the difference between the gate voltage VG and the JFET threshold voltage. The JFET threshold voltage creates a drop of approximately 1V between VG and VOUT, preventing the output voltage of the monitor from rising when the internal MOSFET is turned off until the monitor’s internal MOSFET starts to operate normally.
Figure 5. A traditional supervisor with an external P-JFEF for glitch-free operation
A true glitch-free monitor can sink current through reset, forcing the reset pin to ground potential even when VCC is zero. Figure 6 shows an example circuit of a true glitch-free supervisor, the MAX16161/MAX16162 can achieve glitch-free operation without any external components, making it small and economical.
Figure 6. Application schematic and corresponding timing diagram of the MAX16162
A true glitch-free supervisor IC is no longer just a concept. Designers now have a supervisor IC that generates a reliable reset signal at zero supply voltage, enabling system engineers to use the IC to monitor low-supply (less than 1V) electronics. The MAX16161/MAX16162 are tiny nanoPower ICs with a quiescent current of only 825nA, helping to extend system battery life.
“Reliable voltage supervisor ICs have always been an industry requirement because they can improve system reliability and improve system performance during voltage transients and power failures. semiconductor manufacturers are also continuously improving the performance of voltage supervisor ICs.
“
Reliable voltage supervisor ICs have always been an industry requirement because they can improve system reliability and improve system performance during voltage transients and power failures. Semiconductor manufacturers are also continuously improving the performance of voltage supervisor ICs.
The supervisor IC requires a power-on reset (VPOR) to generate an unambiguous or reliable reset signal, and the state of the reset signal is indeterminate until this minimum supply voltage is reached. Generally, we call this a reset glitch. There are mainly two different topologies for the reset pin, open-drain and push-pull (Figure 1), both of which use an NMOS as the pull-down MOSFET.
Figure 1. Open-Drain and Push-Pull Configurations for Reset Topologies
Figure 2. How the reset voltage is related to the pull-up voltage (VPULLUP) proportionally, resulting in what is commonly referred to as a reset glitch
During power-up, if the supply voltage falls below VPOR, there is not enough voltage to drive the internal MOSFET, so the MOSFET turns off. At this point, the supervisor cannot control the reset voltage. The reset voltage will be the same as the pull-up voltage (VPULLUP) increases proportionally. And once the supply voltage is higher than VPORthe internal MOSFET will drive the RESET pin into an active state.
Voltage supervisors can be used to monitor the low power rails of FPGAs, ASICs or DSPs down to 1V. In low supply voltage processors, I/Os are very sensitive to logic levels and their VIHCan be as low as 0.5V, as shown in Figure 3.
Figure 3. Supervisor Interface to Low Supply Voltage ASIC/FPGA/DSP
During power-up, the FPGA, ASIC, or DSP needs to be in the RESET state until all power rails are stable. When VDD is below VPOR, the RESET pin may experience a glitch that may trigger an unknown state of the FPGA. Once VDD is higher than VPORthe internal MOSFET turns on and connects RESET to GND and causes the RESET pin to output the correct logic low level.
Figure 4. Power-Up Sequence with Glitch Reset Signal
As the electronics industry moves toward low-voltage semiconductors, analog chip makers are also striving to achieve glitch-free monitors based on traditional monitors. Manufacturers can reduce V by improving the processPORbut implementing a truly glitch-free monitor requires an entirely new architecture.
Currently, system engineers use external circuits with traditional supervisors to emulate the glitch-free supervisory function shown in Figure 5. Adding a standard JFET configured as a source follower accomplishes this, and the voltage at the source will depend on the difference between the gate voltage VG and the JFET threshold voltage. The JFET threshold voltage creates a drop of approximately 1V between VG and VOUT, preventing the output voltage of the monitor from rising when the internal MOSFET is turned off until the monitor’s internal MOSFET starts to operate normally.
Figure 5. A traditional supervisor with an external P-JFEF for glitch-free operation
A true glitch-free monitor can sink current through reset, forcing the reset pin to ground potential even when VCC is zero. Figure 6 shows an example circuit of a true glitch-free supervisor, the MAX16161/MAX16162 can achieve glitch-free operation without any external components, making it small and economical.
Figure 6. Application schematic and corresponding timing diagram of the MAX16162
A true glitch-free supervisor IC is no longer just a concept. Designers now have a supervisor IC that generates a reliable reset signal at zero supply voltage, enabling system engineers to use the IC to monitor low-supply (less than 1V) electronics. The MAX16161/MAX16162 are tiny nanoPower ICs with a quiescent current of only 825nA, helping to extend system battery life.
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