“The third-generation mobile communication system (3G) can provide a full range of services from voice to data[1, 2]. The 3G communication network of CDMA2000 is mainly composed of core network (CN), CDMA2000 base station controller (BSC) and base station transceiver system (BTS). A BSC can carry several base stations, each BTS can carry several sector carrier frequencies, the BTS is connected to the BSC through the A bis interface, the BSC is connected to the mobile switching center (MSC) through the A1, A2, and A5 interfaces, and the BSC and the BSC are connected to each other. Using A3 and A7 interfaces, BSC and BTS constitute the access network subsystem BSS.
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Authors: Liu Chunping, An Henan, Xiong Shuijin
1 Introduction
The third-generation mobile communication system (3G) can provide a full range of services from voice to data[1, 2]. The 3G communication network of CDMA2000 is mainly composed of core network (CN), CDMA2000 base station controller (BSC) and base station transceiver system (BTS). A BSC can carry several base stations, each BTS can carry several sector carrier frequencies, the BTS is connected to the BSC through the A bis interface, the BSC is connected to the mobile switching center (MSC) through the A1, A2, and A5 interfaces, and the BSC and the BSC are connected to each other. Using A3 and A7 interfaces, BSC and BTS constitute the access network subsystem BSS. The system clock is required to be synchronized with GPS or GLONASS. When the external synchronization fails, the system local clock maintains the following indicators for more than 8h: the transmission frequency tolerance is better than ±0.05×10 -6, the pilot frequency time calibration error is less than 10ms, and all CDMA channels of the base station are the same as the base station. The time error is less than 1ms, and the phase error from the pilot channel to the code channel is not less than 0.05rad.
2 System clock synchronization scheme
In order to meet the above requirements, a two-stage clock phase-locked loop scheme is adopted. The first-stage phase-locked loop uses the GPS second pulse as the reference frequency, and uses software algorithms to cooperate with hardware phase-locking to generate a control voltage to control the oscillation frequency of the constant temperature crystal oscillator (OCXO) to generate a 10MHz signal; the second-stage phase-locked loop uses 10MHz as the reference source. , synthesizing other clocks of the system, such as 16 fc and 48 fc, by means of hard phase locking. The 2s reference signal of the system is obtained by dividing the frequency by 16 fc, and at the same time, the GPS_2s signal is obtained by dividing the frequency of the GPS second pulse by 2, which is used to adjust the phase of the 2s, so that it can make another phase correction with the GPS second pulse. The local 10MHz adopts constant temperature crystal oscillator, the frequency stability in the temperature range of 0~60℃ is ±0.01×10-6, the aging rate is better than ±0.0005×10-6, and the stability of ±0.05×10-6 and 8h are fully satisfied with the agreement. the hold time requirement. The two-stage phase-locked loop scheme for system synchronization is shown in Figure 1. The first-stage main phase-locked loop GPS/GLONASS receiving card outputs the standard second signal and the OCXO output 10MHz signal for phase detection through the EPLD digital phase detector, and outputs an 8-bit signal. difference. The CPU system reads the difference value, and outputs a 16-bit digital tuning voltage to the D/A converter through a certain control algorithm, and the D/A turns it into an analog quantity to control the change of the OCXO frequency. The advantage of adopting this scheme is that the long-term stability of the output frequency is guaranteed by the GPS standard second signal, while the short-term stability depends on the OCXO constant temperature crystal oscillator.
3 Digital phase detector circuit
The digital phase detector circuit is shown in Figure 2. Its core is a counter with a bit width of 8 bits. The 16 fc signal output by the second-stage phase-locked loop is a counting pulse. At the same time, 16 fc is used as a clock to collect the rising edge of the GPS_1S signal as the synchronous clearing signal of the counter. The Sclr signal is also used as the latch signal of the phase detection value; the counter is cleared after the phase detection value is latched; PD_INT is the phase detection interrupt signal; PD_CLR_EN is the software clearing enable signal. The actual working process is as follows: the phase detection value is latched on the rising edge of each GPS second pulse, and an interrupt request is sent to the CPU at the same time, the CPU responds to the interrupt to read the phase detection value, and the Sclr signal also clears the counter at the same time.
4 2S generation circuit
This module generates the reference clock 2s signal of the BTS system, and also generates 0.1s for the fault detection circuit. Since 16f c is a clock obtained by a two-stage phase-locked loop with the GPS_1s signal as a reference, it combines the long-term stability of the GPS signal and the short-term stability of the 10M OCXO, so the 2s signal is obtained by dividing the frequency by 16fc, not by GPS_1s It is directly obtained by dividing by 2. Figure 3 shows the frequency divider circuit. Since the frequency of 16fc is divided into 2s, and the frequency division ratio is 1.96608×107, a counter with a bit width of 26bit is used to count the rising edge of 16fc. When the synchronous setting terminal sload is “1”, the next The rising edge of 16 fc puts 13893632 into the counter. When the counter counts to 53215231, a positive sload pulse is output on the falling edge of 16 fc, and the counter is set to 13893632 again to start counting again. In this way, the 2S signal can be obtained at the highest data bit q25 of the counter, and the 0.1s signal can be obtained at q21. In addition to being detected and controlled by 53215231, Sload can also be controlled by software and phase difference detection. Figure 4 shows the simulation waveforms of 2s and 0.1s signals.
5 Phase difference detection control circuit
The 2s signal output by the circuit in Figure 3 has high stability, but in order to prevent phase drift, the phase detection control circuit shown in Figure 5 is designed. The software control signal soft_clr is used as the switch of GPS_s signal. When the software outputs a rising edge, the GPS_s signal is XORed with the 2s signal after frequency division by 2, that is, the phase difference between the two is detected. When the phase difference is greater than the specified threshold, a narrow pulse detout is output to control the D flip-flop in Figure 6, so that the rising edge signal of GPS_2s is output to the sload terminal of the counter in Figure 3 to re-control the setting of the counter . If the phase difference is smaller than the specified threshold, the circuit in Fig. 5 does not output the control pulse, and the original phase is maintained for 2s.
The circuit in Fig. 6 is composed of a rising edge detection circuit of GPS_2s and a switch circuit controlled by detout, and the pulse width of the output sload signal is controlled to be half a cycle of 16 fc. Fig. 7 is the simulation waveform of the circuit of Fig. 5 and Fig. 6.
6 Conclusion
This paper presents a solution for CDMA2000 BTS clock synchronization, which mainly provides clocks with frequencies of 10MHz, 2s, 16 fc and 48 fc for the system. This solution enables the output clock to have the long-term stability of GPS/GLONASS received signals and the short-term stability provided by OCXO, fully satisfying the synchronization accuracy specified by the CDMA2000 protocol. The entire digital logic circuit uses an EPM7256AETC100-5 from ALTERA Company. The scheme has been used in practical projects.
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